We are seeking an experienced engineer with a strong background in L2/Shared Cache verification, dedicated to working on cutting-edge high-performance CPUs. In this role, you'll contribute to the functional and performance verification of a server-class L2/Shared Cache unit from scratch, collaborating closely with Architecture and RTL teams. You will be responsible for developing detailed verification plans, building reusable testbench components in SV, UVM, and C++, and driving pre-silicon, emulation, and post-silicon verification efforts. If you're passionate about CPU microarchitecture and delivering high-quality results, this is the opportunity for you.

This role is based out of our Bangalore office.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities:

• Functional and performance verification of the L2/Shared Cache unit for a from-scratch high performance CPU while working closely with Architecture and RTL team
• Develop detailed block level verification plans for L2/Shared Cache that includes both architectural (RISCV ISA) and microarchitectural functionality
• Design and develop reusable block level testbench components in SV, UVM and C++, that include microarchitectural models, monitors, checkers
• Develop random and directed stimulus that spans pre-silicon, emulation and post-silicon domain
• Evaluate and integrate open-source toolchains into the DV flow
• Develop DV environment, tools and infrastructure to enable functional verification for pre-silicon, emulation and post-silicon
• Work with design, test and post silicon validation teams to ensure high quality delivery of the L2/Shared Cache block

Experience & Qualifications:

• BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of experience
• Strong background and experience with high performance OOO CPU microarchitecture especially with load/store, caches and memory subsystem
• Experience working on an x86, ARM or RISCV based CPU
• Architectural understanding of address translation, memory ordering, cache coherence protocols, memory consistency, multi-processors and fabric topologies
• Significant experience debugging RTL and DV in a simulation environment
• Verification methodologies and techniques – Simulation/debug, TB development, stimulus, checking, coverage, infrastructure, tools
• Experience with C++ / SV / UVM as well as scripting languages
• Experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator)
• Strong problem solving and debug skills across various levels of design hierarchies

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government.

As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and supporting documentation will be required and considered as a condition of employment.

If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.