Experienced DV engineer working on RISCV CPU SoC verification. Tasks will be vary over time and will include: test-plan execution, triage & debug, coverage analysis, directed and random test development, DV environment development, scripting & execution analysis, functional & performance verification and more.

This role is hybrid, based out of Boston, MA or, potentially, Toronto, Ontario.

Responsibilities:

• Functional (& performance) verification of various aspects of the SoC, working at both the SoC level or the IP/SubSystem level (or both).
• Develop detailed SoC/IP/Subsystem level testplans. Develop complementary coverage plans.
• Design and develop reusable testbench components using SV-UVM (and C++/DPI - possibly python as well). Components may include: microarchitectural models, monitors/trackers, checkers, tests & test stimulus (tests, sequences, sequencers, drivers), BFMs, coverage monitors, assertions, etc.
• Develop stimulus spanning the spectrum from directed to fully random.
• Integrate, enable and utilize various VIPs.
• Evaluate and integrate open-source toolchains into the DV flow.
• Develop DV environment, tools and infrastructure to enable functional verification for pre-silicon, emulation and post-silicon
• Work with design/architecture, test and post silicon validation teams to ensure high quality delivery of the SoC.

Experience & Qualifications:

• BS/MS/PhD in EE/ECE/CE/CS with 2 years of experience. Experience with high performance OOO CPU microarchitectures, especially with load/store, caches & memory subsystem, and PCIE/IO subsystems.
• Knowledge of industry standard protocols: PCIe, CXL, SPI, I3C, I2C, CHI, AXI & APB.
• Architectural understanding of overall processor architecture (CPU + IO), boot flows, ROM generation, power-management operation, interrupts & errors.
• Experience debugging RTL and DV in a simulation environment
• Experience developing SV-UVM testbench environments and components.
• Scripting languages (python, perl)
• Experience with hardware description languages (System Verilog) and simulators.
• Strong problem solving and debug skills across various levels of design hierarchies

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government.

As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and supporting documentation will be required and considered as a condition of employment.

If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.