CPU RTL Engineer, Shared Cache



Santa Clara, CA, USA
Posted on Thursday, February 22, 2024

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Tenstorrent is looking for a leadership level Cache RTL design engineer to join this innovative team as a technical expert. In this role, the candidate will develop and implement the highest performance, most energy efficient cache and fabric designs in the industry. This person will be a key contributor for developing Tenstorrent’s next generation of cores and caches. This role requires creativity and innovation, along with excellent verbal and written communication skills. The ideal candidate has strong analytical thinking and problem-solving skills and enjoys using those skills to accomplish goals.

This role is Hybrid, based out of Austin,TX, Santa Clara, CA, or Fort Collins, CO.


  • RTL coding in Verilog leveraging on both industry tools as well as open-source infrastructure
  • Play a lead role in the architecture, design and development of processor L2 and LLC (Last Level Cache) for high-performance computing systems.
  • Design and micro architect Caches as driven by capacity, latency, bandwidth, and RAS requirements
  • Drive trade-offs for your logic by working closely with performance, DV and physical design engineers to craft optimal solutions that meet the design goals
  • Deploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL and evaluate synthesis, timing and power results
  • Debug RTL/logic issues across various hierarchies (ex: core, chip) in both pre-silicon and post-silicon environment

Experience & Qualifications:

  • BS/MS/PhD in EE/ECE/CE/CS with at least 10 years of experience
  • Experience in Cache, Multi-processor coherency microarchitecture, familiarity with AXI, TileLink and CHI protocol
  • Experience with computer architecture/system components/network/fabrics as a part of a CPU, ASIC or SOC design team
  • Expertise in logic design and ability to evaluate functional, performance, timing and power for you design
  • Strong experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator)
  • Experience with NuCA NuMA (Non-uniform Cache Memory architecture) architectures and implementations.
  • Expertise in microarchitecture definition and specification development
  • Prior experience in industry standard ISAs – ARM, RISC-V, X86 preferred
  • Strong problem solving and debug skills across various levels of design hierarchies

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been sanctioned by the U.S. government.

As this position will have direct and/or indirect access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency information and/or documentation will be required and considered as Tenstorrent moves through the employment process.