Staff Engineer, CPU Core Feature Verification and Debug

Tenstorrent

Tenstorrent

Austin, TX, USA
Posted on Thursday, February 22, 2024

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We are looking for a CPU core level feature / testplan verification engineer responsible for ISA and microarchitectural verification.

This role is hybrid, based out of Austin, TX or Santa Clara, CA.

Responsibilities:

  • Functional verification with emphasis on core level testplanning, stimulus development and regression debug for simulation and emulation regressions
  • Understand ISA and microarchitectural specifications for the Core and create comprehensive testplans
  • Hands-on debug for core level failures. Propose and implement stimulus enhancements and debug capability improvements for core, cluster and chip level testbench environments
  • Develop architectural and microarchitectural coverage for core features and create stimulus for closing coverage in a timely manner
  • Support design deployment across simulation and emulation platforms
  • Develop random and directed stimulus that spans pre-silicon, emulation and post-silicon domain
  • Work with design, test and post silicon validation teams to ensure high quality delivery of the entire CPU core / cluster

Experience & Qualifications:

  • BS/MS/PhD in EE/ECE/CE/CS with at least 3 years of experience
  • Strong background and experience with high performance OOO CPU microarchitecture
  • Experience and understanding of one or more ISAs - x86, ARM or RISCV
  • Experience debugging RTL and DV in a simulation environment, proficient at waveform and log file based debug
  • Experienced with assembly, C/C++ and UVM based stimulus generation targeting both ISA and microarchitectural scenarios
  • Familiar with simulation, formal and emulation environments
  • Hands-on with scripting (Python, PERL)
  • Experience with hardware description languages (Verilog, VHDL) and simulators (VCS, NC, Verilator)
  • Strong problem solving and debug skills across various levels of design hierarchies

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

Due to U.S. Export Control laws and regulations, Tenstorrent is required to ensure compliance with licensing regulations when transferring technology to nationals of certain countries that have been licensing conditions set by the U.S. government.

Our engineering positions and certain engineering support positions require access to information, systems, or technologies that are subject to U.S. Export Control laws and regulations, please note that citizenship/permanent residency, asylee and refugee information and/or documentation will be required and considered as Tenstorrent moves through the employment process.

If a U.S. export license is required, employment will not begin until a license with acceptable conditions is granted by the U.S. government. If a U.S. export license with acceptable conditions is not granted by the U.S. government, then the offer of employment will be rescinded.