Physical design for high-performance designs going into industry leading AI/ML architecture. The person coming into this role will be involved in all implementation aspects from synthesis to tapeout for various IPs on the chip. The work is done alongside a group of highly experienced engineers across various domains of the AI chip.

This role is hybrid, based out of Santa Clara, CA, Austin, TV, or Ft. Collins, CO.

Responsibilities:

• Own physical design partitions and drive the design to closure
• Define PD requirements by working closely with the front-end team, understand the chip architecture and drive physical aspects early in the design cycle
• Physical design tasks including such as synthesis, PnR, timing closure, area improvement, floorplanning, clocking, I/O planning and power optimization
• Deploy innovative techniques for improving power, performance and area of the design, drive experiments with RTL, and evaluate synthesis, timing and power results
• Collaborate with RTL designers to explore design options, conduct PD experiments, analyze results, understand tradeoffs and arrive at optimal design solutions

Experience & Qualifications:

• BS/MS/PhD in EE/ECE/CE/CS
• Expertise in optimizing PPA for high performance and low power designs
• Excellent understanding of logic design fundamentals and gate/transistor level implementation
• Prior experience with optimizing RTL for timing/power
• Hands-on experience with synthesis, block and chip level implementation, timing closure and ECO flows
• Knowledge of low-power design flows such as power gating, multi-Vt and voltage scaling
• Prior experience working on high performance technology nodes and understanding of deep sub-micron design problems/solutions
• Strong programming skills in Tcl/Perl/Shell/Python
• Knowledge of CPU or AI/ML Accelerator Micro Architecture is a plus
• Exposure to DFT is an asset